Category:Logic gates

**논리 회로**
	computational equipment, physical or theoretical, that performs a boolean logic function
	미디어 올리기
	위키백과
다음의 하위 개념임	electrical element;
다음의 한 부분임	logic circuit;
전거 통제
	Q170451; GND ID: 4135908-2; NDL 전거 ID: 01088538; BabelNet ID: 00037487n
	Reasonator; Scholia; Wikidocumentaries; PetScan; 통계학; WikiMap; Locator tool; 관련 KML이 들어있는 문서; Search depicted;

이 분류는 하위 분류로 연결되는 메인 분류입니다. 가능한 한 많은 미디어 파일들이 적절한 하위 분류에 들어가야 합니다. 필요하다면 새로운 하위 분류를 만들 수도 있습니다. 그림들은 분류화되어 여러가지 분류에 속해 있어야 합니다. 더 많은 분류들을 찾고 싶다면 대문과 분류를 확인하세요.

English: Logic gate is a device,that works on the principle of the logic relationship between the signals of input and output voltages.This category holds description of logic functions on an abstract level, without committing to a particular technology for their implementation. For the latter, see Category:Digital logic by family. Note that there are other techniologies than electronics to implement a logic gate, e.g. en:Fluidics.

<nowiki>puerta lógica; Rökrás; Get logik; Логически елемент; Mantıksal kapı; منطقی گیٹ; Logické hradlo; логічний вентиль; 邏輯閘; Dergehê mantiqî; 논리 회로; logikpordo; Логичко коло; Logička kola; লজিক গেট; fonction logique; logički sklopovi; Cổng logic; Loģiskais elements; Logiese hek; Логичка капија; Logic gates; 逻辑门; Logisk port; Məntiqi element; 邏輯門; logic gate; بوابة منطقية; 邏輯門; logikai kapu; ኆኅተ አመክንዮ; Ate logiko; porta lògica; Logikgatter; Porta logega; Տրամաբանական տարրեր; 邏輯閘; Gate; ლოგიკური ვენტილი; 論理回路; بوابات منطقية; තර්කන ද්වාර; Porta logica; लॉजिक गेट; 逻辑门; Looginen portti; தருக்கப் படலை; porta logica; ਲੌਜਿਕ ਗੇਟ; Loogiline värav; 逻辑门; Puerta lógica; Logisk grind; 邏輯閘; porta lógica; ลอจิกเกต; Logička kapija; Ganghaan lohika; logische poort; دروازه منطقی; Loginis elementas; logična vrata; שער לוגי; 逻辑门; логический вентиль; Gerbang logika; Bramka logiczna; ലോജിക് ഗേറ്റ്; Logička kapija; Dergehê mantiqî; Poartă logică; 邏輯門; Логичка капија; Porta lóxica; Logický člen; Λογική πύλη; دەرگەهێ مانتقی; tipo di variabile booleana; デジタル回路によって論理演算や記憶を行う回路; fonction élémentaire utilisée en électronique numérique; digital krets vars utgång är en logisk funktion av ingångarna; Eragiketa boolear sinple bat egiten duen zirkuitu elektronikoa.; מבצע פעולות באלגברה בוליאנית; элемент цифровой схемы, выполняющий элементарную логическую операцию; logikai alap vagy ezek kombinációját megvalósító áramkörök; elektrisches Bauelement; computational equipment, physical or theoretical, that performs a boolean logic function; computational equipment, physical or theoretical, that performs a boolean logic function; component electrònic que es pot utilitzar per conduir l'electricitat basada en una regla; základní stavební prvek logických obvodů; dispositivo electrónico que opera una función booleana u otra función como sumar o restar; Compuerta logica; Puerta Logicas; Puerta logica NOT; Puerta lógica NOT; Puerta SI; XNOR; Compuerta lógica; Puerta logica; NOT; AND; IF; Compuertas lógicas; Compuertas logicas; Puerta lóhica; Puerta lohica; circuit logique; fonctions logiques; porte logique; Rökrásir; Portes lògiques; Nand-gate; Exclusive-or-gate; Nor-gate; Gatter; DIN 40700; Logische Gatter; Schaltgatter; Logisches Gatter; Boolesches Gatter; Portas lógicas; Porta logica; Circuito lógico; Lógica digital; Circuitos lógicos; porta logica; Λογικές πύλες; دروازه‌های منطقی; دروازهٔ منطقی; گیت‌های منطقی; مدار منطقی; مدارهای منطقی; گیت منطقی; 邏輯門; 逻辑电路; 逻辑门; 逻辑闸; Logicka kapija; Логичка врата; Логичко коло; Mantık kapısı; Mantıksal kapılar; Lojik kapılar; ロジック回路; 論理ゲート; Circuit logic binar; Circuite logice binare (digitale); Logiska grindar; Grind; Logic Gate; วงจรตรรก; ลอจิกเกท; เกต; วงจรตรรกะ; ประตูสัญญาณตรรกะ; 논리회로; 논리게이트; 논리 게이트; Logic gate; schakelalgebra; logische schakeling; NI; XILI; NILI; Logička vrata; NE; तर्क द्वार; තාර්කික ද්වාරවල පසුබිම; තාර්කික ද්වාර; OR-piiri; Logiikkapiiri; Logiikkaportti; Porttipiiri; Loogiset portit; AND-piiri; NOT-piiri; digital logic gate; Boolean logic gate; logic circuit element; gate; منطقية; المنطقيه; التحكم المنطقى; الدارات المنطقية; بوابات المنطقية; الدوائر المنطقية; المنطقية; البوابات المنطقية; تحكم منطقي; البوابة المنطقية; بوابات منطقية; البوابات المنطقية الاساسية; بوابه منطقيه; البنية البوابية; Logický prvek; Logické členy; Logické hradlo; Hradlo; தருக்க படலை</nowiki>

하위 분류

다음은 이 분류에 속하는 하위 분류 20개 가운데 20개입니다.

Logic gates by type‎ (3 C)

I

IMPLY gates‎ (1 C, 11 F)

M

Majority gate‎ (1 C, 2 F)

N

NAND gates‎ (38 C, 83 F)
NOR gates‎ (16 C, 1 P, 70 F)
NOT gates‎ (29 C, 36 F)

O

OR gates‎ (10 C, 68 F)
OR-AND-Invert gates‎ (2 F)

S

Sheffer stroke‎ (1 C, 5 F)

X

XNOR gates‎ (3 C, 22 F)
XOR gates‎ (7 C, 46 F)

Y

YES gates‎ (27 C, 15 F)

"Logic gates" 분류에 속하는 문서

이 분류에는 문서 1개만이 속해 있습니다.

N

Template:NOR Logic

"Logic gates" 분류에 속하는 미디어

다음은 이 분류에 속하는 파일 192개 가운데 192개입니다.

1pWebbt.jpg 487 × 235; 22 KB
2 NAND gates with 2 variables.jpg 590 × 302; 106 KB
2 NAND gates with 2 variables.svg 512 × 239; 528 바이트
2 NOR gates with 2 variables.jpg 698 × 282; 122 KB
2bsumsd.jpg 962 × 356; 66 KB
2bwebb2l.jpg 395 × 270; 17 KB
3 NAND gates with 2 variables.jpg 822 × 528; 288 KB
3 NOR gates with 2 variables.jpg 792 × 522; 262 KB
3b inv Luk.jpg 114 × 79; 3 KB
3b inv NOT+.jpg 114 × 79; 3 KB
3b inv NOT-.jpg 114 × 79; 3 KB
3b inv ROTB.jpg 114 × 79; 3 KB
3b inv ROTF.jpg 114 × 79; 3 KB
3b9rrg.jpg 180 × 606; 21 KB
3balu.jpg 379 × 864; 68 KB
3BDet=20.jpg 171 × 158; 7 KB
3bps.jpg 770 × 356; 49 KB
3bpsl.jpg 770 × 427; 58 KB
3D Peer AND Gate.png 160 × 75; 931 바이트
3D Peer NOT Gate & equivalent NOT gates.png 1,261 × 311; 87 KB
3D Peer NOT Gate.png 160 × 86; 1 KB
3D Peer OR Gate.png 160 × 75; 1 KB
3D Peer XOR Gate.png 160 × 75; 1 KB
A igual B 4btis grande.png 474 × 304; 9 KB
A mayor que B grande.png 593 × 348; 10 KB
A YES molecular logic gate.png 1,179 × 1,080; 17 KB
ABEL-DOT-Extensions .gif 406 × 159; 5 KB
ABEL-DOT-Extensions.gif 794 × 1,123; 8 KB
An integrated logic gate by A. Coskun.png 1,547 × 936; 18 KB
AND gate.png 734 × 194; 6 KB
And-inverter-graph.png 851 × 527; 45 KB
AND-NOT-OR-Gatter.jpg 659 × 172; 12 KB
AOAI gate with colorboxes.svg 511 × 391; 32 KB
Arba is ir ne.png 169 × 161; 2 KB
Baops.gif 787 × 593; 24 KB
Baopscn.gif 787 × 593; 24 KB
Cascaded-AND-OR-diode-logic.svg 120 × 110; 12 KB
Circuit 2.png 732 × 331; 18 KB
Circuit elements-fr.png 400 × 260; 21 KB
Circuit elements.png 400 × 260; 12 KB
Circuito 3.png 250 × 49; 4 KB
Circuito4.png 250 × 49; 4 KB
Circuito5.png 201 × 61; 5 KB
Comb logic tseitin.svg 452 × 182; 84 KB
Conductanve vs Gate Voltage.png 399 × 271; 7 KB
ConductanvevsGate Voltage.png 399 × 271; 9 KB
ConductanvevsGate VoltageCorrected.png 399 × 271; 9 KB
Converting a NAND gate to an AND gate.png 1,745 × 877; 17 KB
CPT-logic-gate ex3 - Answer.svg 398 × 88; 44 KB
Depletion-load NMOS logic (NOT).png 503 × 639; 13 KB
Diagram and chart of a logic gate.jpg 816 × 252; 29 KB
Digital-gates.png 1,024 × 1,024; 77 KB
DigitalInverter.png 386 × 382; 6 KB
Diode-OR.png 267 × 112; 910 바이트
ECL structure 1000.jpg 1,000 × 714; 106 KB
Ejemplo computo GRAFCET.PNG 266 × 275; 5 KB
Electronic-component-ICS.png 813 × 792; 8 KB
Engin Umut Akkaya - Reaction mechanism.JPG 2,000 × 2,921; 3.97 MB
Enhancement-load NMOS logic (NOT).png 498 × 631; 13 KB
Fault dominance example.png 402 × 288; 11 KB
Fault Equivalence Example.png 994 × 477; 75 KB
Fault equivalence example.png 1,205 × 529; 94 KB
Figura0001.jpg 400 × 130; 10 KB
Figura0005.jpg 350 × 66; 6 KB
Figure 1. Block structure of a dual-input combinational molecular logic gate.png 771 × 256; 27 KB
Fonctions logiques(6-d).png 240 × 420; 5 KB
Fonctions logiques(7-a).png 161 × 62; 29 KB
Fonctions logiques(7-d).png 240 × 420; 5 KB
Fonctions logiques(9-3).png 400 × 195; 4 KB
FPGAEtShields10.png 700 × 345; 68 KB
FPGAEtShields11.png 631 × 202; 46 KB
G4QF-intersectionals.png 1,206 × 1,059; 82 KB
IIL circuit.png 778 × 578; 21 KB
IMPLY gate NAND.png 291 × 120; 4 KB
INHIBIT molecular logic gate by Gunnlaugsson.png 944 × 1,280; 22 KB
JA-Loogika tabel.png 220 × 107; 887 바이트
JA-loogikaelement.png 740 × 688; 16 KB
Kiikku or not and gates.png 554 × 312; 10 KB
Kokonaissummain.PNG 411 × 268; 6 KB
Kontakt.PNG 320 × 256; 3 KB
LAB VHDL Tiny861 7.png 784 × 619; 117 KB
Log-i.JPG 250 × 250; 6 KB
Logic circuit example.png 385 × 231; 12 KB
Logic schematic 001.jpg 1,212 × 1,080; 695 KB
Logic schematic 002.jpg 1,248 × 882; 657 KB
Logic schematic 003.jpg 1,146 × 837; 600 KB
Logic-gates-circuits.png 2,550 × 3,300; 255 KB
Logical-basic-gates.jpg 884 × 646; 96 KB
LogicGatesWorking.png 350 × 300; 15 KB
Logiksysteme 1.JPG 830 × 543; 51 KB
LogiqueTD2fig1.png 575 × 171; 24 KB
LogiqueTD2fig2.png 452 × 115; 11 KB
LogiqueTD7fig1.png 297 × 142; 24 KB
LogiSim Screenshot 1.png 1,320 × 755; 57 KB
Lógica Cableada Funciones Lógicas.GIF 912 × 603; 19 KB
Lógica Cableada Relé auto mantenido y flip flop.GIF 865 × 380; 9 KB
MI-grind.PNG 162 × 80; 995 바이트
MIL symbols (AND, OR, Amp, status description symbol).PNG 600 × 1,560; 82 KB
Moleculators de silva13 02.png 917 × 462; 8 KB
NAND gate with 1 variable.jpg 426 × 243; 63 KB
NAND gate with 1 variable.svg 512 × 410; 347 바이트
Negative-Positive Logic (5 gates).PNG 873 × 451; 35 KB
NOR gate with 1 variable.jpg 440 × 238; 82 KB
Operatori logici.PNG 366 × 721; 26 KB
Portada2 puertas.jpg 728 × 546; 150 KB
Portais lógicos.png 674 × 720; 63 KB
Porte logique OU (jeu de la vie).jpg 202 × 267; 8 KB
Porte logique OU EXCLUSIF.jpg 189 × 256; 8 KB
Puerta 0.svg 300 × 100; 5 KB
Puerta 1.svg 300 × 100; 5 KB
Puerta AND biología sintética.png 1,065 × 236; 73 KB
Puerta AND con transistores.jpg 607 × 360; 15 KB
Puerta AND.svg 300 × 100; 5 KB
Puerta BUF.svg 300 × 100; 3 KB
Puerta CM.svg 300 × 100; 5 KB
Puerta CMI.svg 300 × 100; 5 KB
Puerta INU.svg 300 × 100; 4 KB
Puerta lógica 001.svg 150 × 75; 4 KB
Puerta lógica 002.svg 150 × 75; 5 KB
Puerta lógica 003.svg 150 × 75; 5 KB
Puerta lógica 004.svg 150 × 75; 5 KB
Puerta lógica 011.svg 150 × 75; 4 KB
Puerta lógica 012.svg 150 × 75; 5 KB
Puerta lógica 013.svg 150 × 75; 5 KB
Puerta lógica 014.svg 150 × 75; 6 KB
Puerta lógica NAND biología sintética.png 1,065 × 236; 72 KB
Puerta lógica OR biología sintética.png 1,065 × 236; 77 KB
Puerta NAND con transistores.jpg 299 × 387; 8 KB
Puerta NAND.svg 300 × 100; 5 KB
Puerta NCM.svg 300 × 100; 5 KB
Puerta NCMI.svg 300 × 100; 5 KB
Puerta NOR.svg 300 × 100; 5 KB
Puerta OR.svg 300 × 100; 5 KB
Puerta XNOR.svg 300 × 100; 5 KB
Puerta XOR.svg 300 × 100; 4 KB
Puertas lógicas de circuitos.jpg 640 × 400; 44 KB
Pull-Up-Down-Tristate.png 535 × 510; 10 KB
Pull-Up-Down-Tristate.svg 535 × 510; 22 KB
RotaxaneLogicGate.png 526 × 401; 6 KB
S-MOS Systems ASIC SLA6140.jpg 2,409 × 2,445; 7.17 MB
Single and two qubit gate.png 1,182 × 799; 697 KB
Snap Circuit U20 - XOR Gate Internal.jpg 2,592 × 1,936; 1.21 MB
Table 1. Select single-input logic gates with truth tables.png 926 × 429; 14 KB
Table 2. Select dual-input logic gates with truth tables.png 975 × 345; 36 KB
Td1bfig1.png 564 × 164; 15 KB
Td1bfig2.png 697 × 158; 14 KB
Td1bfig3.png 385 × 110; 5 KB
Td1bfig4.png 292 × 104; 4 KB
Td2bfig1.png 724 × 178; 14 KB
Td2bfig2.png 409 × 239; 11 KB
Td3bfig1.png 219 × 147; 4 KB
Td3bfig2.png 232 × 146; 5 KB
Td3bfig3.png 365 × 235; 17 KB
Td4bfig1.png 468 × 309; 16 KB
Td4bfig5.png 540 × 184; 17 KB
Td5bfig2.png 684 × 315; 29 KB
Td5bfig3.png 523 × 250; 30 KB
Td7bfig0.png 613 × 197; 20 KB
Td7bfig1.png 327 × 210; 10 KB
Td7bfig2.png 621 × 226; 16 KB
Td7bfig3.png 357 × 150; 13 KB
Td7bfig4.png 480 × 157; 15 KB
Td7bfig5.png 432 × 147; 12 KB
Td8fig1.png 193 × 66; 2 KB
Td8fig2.png 238 × 60; 3 KB
Td8fig3.png 583 × 121; 9 KB
Td8fig4.png 238 × 180; 8 KB
Td8fig5.png 545 × 291; 19 KB
TP1 exo1.png 500 × 155; 16 KB
TP2 exo3 DE.png 543 × 297; 69 KB
Tp3exo2 Excess3.png 422 × 401; 35 KB
Tp3exo3 Comp.png 499 × 224; 28 KB
Tp5 exo2.png 626 × 368; 56 KB
Tp6 exo2.png 660 × 213; 45 KB
Tp6 exo4.png 428 × 232; 54 KB
Tp6 exo5.png 660 × 198; 38 KB
Trehbitnaja1.jpg 114 × 79; 2 KB
Trehbitnaja2.jpg 114 × 79; 2 KB
Trehbitnoe=.jpg 114 × 79; 3 KB
Trehbitnyi0.jpg 114 × 79; 2 KB
TTL2.png 320 × 256; 4 KB
Tuple1.tif 430 × 290; 7 KB
Tuple10.tif 648 × 328; 17 KB
Tuple11.tif 420 × 270; 21 KB
Tuple2.tif 668 × 287; 15 KB
Tuple3.tif 742 × 479; 22 KB
Tuple4.tif 902 × 465; 24 KB
Tuple6.tif 717 × 165; 10 KB
Tuple7.tif 685 × 215; 17 KB
Tuple8.tif 953 × 303; 23 KB
Tuple9.tif 883 × 350; 26 KB
VÕI-loogikaelement.png 806 × 648; 6 KB

Category:Logic gates

하위 분류

*

A

C

E

I

M

N

O

S

X

Y

"Logic gates" 분류에 속하는 문서

N

"Logic gates" 분류에 속하는 미디어

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