File:Cmos-chip structure in 2000s (en).svg

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Cmos-chip_structure_in_2000s_(en).svg‎ (SVG file, nominally 550 × 810 pixels, file size: 85 KB)

[edit] Summary

Description

Schematic structure of a CMOS chip, like it is build in the early 2000s. The grafic shows LDD-MISFET's on a SOI silicon substrate with five metallization layers and solder bump for flip-chip bonding. Also it shows the section for FEOL (front-end of line), BEOL (back-end of line) and first parts of back-end process. (translated german version)
Date

9.12.2006
Source

self made (from university scripts and scientific papers)
Author

Henrik Schumacher
Permission
(Reusing this image)

See below.

[edit] Licensing

I, the copyright holder of this work, hereby publish it under the following licenses:
GNU head Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".

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Date/TimeThumbnailDimensionsUserComment
current18:52, 9 December 2006Thumbnail for version as of 18:52, 9 December 2006550×810 (85 KB)Cepheiden (talk | contribs) ({{Information |Description= Schematic structure of a CMOS chip, like it is build in the early 2000s. The grafic shows LDD-MISFET's on a SOI silicon substrate with five metallization layers and solder bump for flip-chip bonding. Also it shows the section f)
18:49, 9 December 2006Thumbnail for version as of 18:49, 9 December 2006550×810 (85 KB)Cepheiden (talk | contribs) ({{Information |Description= Schematic structure of a CMOS chip, like it is build in the early 2000s. The grafic shows LDD-MISFET's on a SOI silicon substrate with five metallization layers and solder bumb for flip-chip bonding. Also it shows the section f)

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