Category:Digital circuits
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Subcategories
This category has the following 30 subcategories, out of 30 total.
A
C
- CORDIC (19 F)
D
E
- Digital logic equations (20 F)
F
G
- Glitch in digital electronics (36 F)
L
M
- Digital Multipliers (19 F)
P
- Phase frequency detectors (7 F)
R
S
Media in category "Digital circuits"
The following 200 files are in this category, out of 227 total.
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1.SOC.3.A.Gate.Combinational.20130415.pdf 1,654 × 1,239, 8 pages; 62 KB
1.SOC.3.A.Gate.Combinational.20160307.pdf 1,654 × 1,239, 12 pages; 91 KB
1.SOC.3.B.Gate.Sequential.20130415.pdf 1,654 × 1,239, 5 pages; 56 KB
1.SOC.3.B.Gate.Sequential.20160307.pdf 1,654 × 1,239, 10 pages; 77 KB
1.SOC.3.C.Gate.Subsystem.20130415.pdf 1,654 × 1,239, 5 pages; 55 KB
1.SOC.3.C.Gate.Subsystem.20160307.pdf 1,654 × 1,239, 17 pages; 377 KB
1.SOC.3.D.Gate.Delay.20130415.pdf 1,654 × 1,239, 13 pages; 96 KB
1.SOC.3.D.Gate.Delay.20130629.pdf 1,654 × 1,239, 6 pages; 72 KB
1.SOC.3.E.Gate.Power.20130415.pdf 1,654 × 1,239, 17 pages; 104 KB
2-pin Charlieplexing with common resistor.svg 1,053 × 744; 37 KB
2-pin Charlieplexing with individual resistors.svg 744 × 1,053; 40 KB
2BitPermutator.svg 957 × 354; 11 KB
3 Pin Charlieplexing.png 440 × 266; 3 KB
3-pin Charlieplexing matrix with common resistors.svg 744 × 1,053; 151 KB
3-pin Charlieplexing matrix with individual resistors.svg 744 × 1,053; 155 KB
3-pin Charlieplexing with common resistors.svg 1,053 × 744; 118 KB
3-pin Charlieplexing with individual resistors.svg 744 × 1,053; 119 KB
Ackumulator adv.png 500 × 500; 13 KB
Ackumulator adv2.png 500 × 500; 13 KB
Ackumulator adv3.png 500 × 500; 13 KB
Ackumulator adv4.png 500 × 500; 13 KB
Ackumulator simple.png 320 × 256; 5 KB
Adapter BIN6.png 1,145 × 404; 13 KB
ADPC.png 604 × 123; 4 KB
Adressregister.png 320 × 256; 3 KB
Adressregister2.png 320 × 256; 4 KB
Affichage4digits.png 520 × 293; 33 KB
AMD 22V10 Macrocell.jpg 881 × 403; 56 KB
AndOrMatrixExample.svg 901 × 587; 130 KB
Asynchronny citac nahor zlozeny z preklapacich obvodov D.png 1,199 × 337; 12 KB
AT89LV51 diagrama block.png 587 × 732; 37 KB
Atmel avr rs232 resistors.JPG 597 × 274; 22 KB
Autômato previsão de desvios com 2 bits para o histórico.png 400 × 266; 81 KB
Band gap vs E.jpg 1,000 × 750; 67 KB
Bang-Bang phase detector.png 1,058 × 794; 2.41 MB
BascSchmidt.png 253 × 193; 2 KB
BascSchmidt1.png 422 × 220; 2 KB
CC-Simulator.png 1,291 × 997; 123 KB
CDL005W.png 719 × 282; 10 KB
Chase Ligh with 5 Leds.gif 611 × 333; 26 KB
Chase Light with 8-Bit Shift register.gif 480 × 421; 130 KB
Chassis Kits.jpg 344 × 229; 24 KB
Circuit de mise à 1111111...11.png 727 × 280; 10 KB
Circuit qui effectue les opérations FHS, FFS, CLZ et autres.png 723 × 757; 16 KB
Circuit sequencial.JPG 358 × 195; 8 KB
Circuit value problem - animation.svg 200 × 350; 3 KB
Circuit.svg 497 × 179; 35 KB
Circuito elettrico.png 800 × 588; 187 KB
Circuito verifica porta AND.png 672 × 344; 45 KB
Circuito.png 450 × 170; 8 KB
Clock on demand.png 1,158 × 900; 80 KB
Cmosbuff.png 852 × 669; 78 KB
Combinational logic.GIF 264 × 336; 4 KB
Combinatorial Logic Example.svg 452 × 182; 38 KB
Common input of IEC functional block.svg 531 × 354; 6 KB
Conditional Capture.png 830 × 860; 45 KB
Conditional precharge.png 646 × 886; 39 KB
Cpu adv.png 320 × 256; 6 KB
CPU adv.PNG 1,000 × 1,500; 77 KB
CPU adv2.PNG 1,000 × 1,500; 77 KB
CPU AND.PNG 450 × 250; 7 KB
Cpu block2.png 500 × 1,000; 26 KB
Cpu block3 1.png 500 × 1,000; 26 KB
Cpu block3.png 500 × 1,000; 26 KB
Cpu block4.png 500 × 900; 21 KB
Cpu block5.png 500 × 900; 21 KB
CPU D VIPPA.PNG 320 × 256; 3 KB
CPU FA.PNG 300 × 250; 4 KB
CPU IR4 1.PNG 900 × 7,150; 409 KB
CPU IR5 1.PNG 900 × 8,150; 447 KB
CPU IR6 1.PNG 900 × 7,700; 439 KB
CPU JK VIPPA.PNG 320 × 256; 4 KB
CPU Memory Conf.PNG 600 × 400; 17 KB
CPU Memory Conn.PNG 500 × 400; 14 KB
CPU Mnemonics 2.PNG 500 × 800; 35 KB
CPU Mnemonics 3.PNG 500 × 800; 38 KB
CPU PC.PNG 800 × 600; 19 KB
CPU PC2.PNG 800 × 600; 20 KB
CPU Register.PNG 700 × 500; 16 KB
CPU simple.PNG 1,000 × 1,500; 74 KB
CPU simple2.PNG 1,000 × 1,500; 73 KB
CPU simple3.PNG 1,000 × 1,500; 72 KB
CPU simple4.PNG 1,000 × 1,500; 72 KB
CPU simple5.PNG 1,000 × 1,500; 73 KB
CPU simple6.PNG 1,000 × 1,500; 74 KB
CPU SR VIPPA.PNG 320 × 256; 3 KB
CPU SR.PNG 800 × 600; 17 KB
CPU T VIPPA.PNG 320 × 256; 4 KB
CPU testrigg.PNG 1,500 × 1,100; 75 KB
CPU timing4.PNG 300 × 256; 6 KB
CPU Transistor.PNG 300 × 250; 3 KB
CpucrPinout.png 715 × 509; 20 KB
Crossover nand svg.svg 478 × 230; 38 KB
Crossover nand.pdf 795 × 383; 22 KB
Crossover xor.gif 895 × 910; 6 KB
CurrentSwitchLogic.svg 1,052 × 744; 132 KB
CyOut MUX2s.png 756 × 443; 7 KB
D-триггер с динамическим тактированием.PNG 308 × 457; 12 KB
Data Transition Look Ahead.png 1,348 × 854; 87 KB
Dataregister.png 320 × 256; 4 KB
Dataregister2.png 320 × 256; 5 KB
Dataregister4.png 330 × 256; 6 KB
DCC Decoder.jpg 640 × 480; 115 KB
Dds frequency-8 14.svg 512 × 384; 16 KB
Dds.svg 653 × 248; 19 KB
Detector de flanco de bajada.JPG 512 × 384; 21 KB
Diagrama bloc.jpg 777 × 841; 113 KB
Digital buffer.svg 354 × 177; 2 KB
Digital clock.png 822 × 505; 39 KB
Diode logic for transistor clock.jpg 1,632 × 2,564; 526 KB
Direct digital synthesizer block diagram.png 539 × 280; 11 KB
DPCM irudi 1.png 589 × 270; 13 KB
DPCM laginaren aurreikuspena.png 528 × 336; 14 KB
Dpcm sistesi bidezko azterketa.png 487 × 386; 12 KB
DZTL.png 320 × 256; 4 KB
ECC NASA standard coder.svg 842 × 595; 9 KB
ECL.svg 851 × 661; 55 KB
Enand gate.svg 1,390 × 409; 6 KB
Entprellte Taste.svg 628 × 603; 11 KB
Entradas possíveis.jpg 2,451 × 340; 99 KB
Es1 Sistemi01.JPG 1,058 × 488; 42 KB
Es1 Sistemi02.JPG 586 × 504; 30 KB
Example circuitry.jpg 467 × 982; 86 KB
Exor and FF comparator for NRZ data.png 982 × 600; 47 KB
Exor phase comparator of clocks.png 1,123 × 794; 2.55 MB
Foto circuito.jpg 1,310 × 733; 209 KB
Four-Bit Majority Circuit.png 390 × 215; 2 KB
Ground Bounce.svg 450 × 375; 28 KB
Ground loop - balanced line.svg 949 × 514; 54 KB
Ground loop - common impedance coupling.svg 944 × 517; 46 KB
Ground loop - electromagnetic fields.svg 958 × 576; 51 KB
Ground loop - ground lift.svg 1,100 × 510; 50 KB
Ground loop - isolation transformer.svg 961 × 534; 31 KB
Ground loop - leakage currents simplified.svg 1,275 × 523; 43 KB
Ground loop - parasitic elements.svg 940 × 569; 45 KB
Ground loop - signal circuitry fixed.svg 1,120 × 516; 63 KB
Ground loop - signal circuitry raw.svg 1,120 × 516; 62 KB
HCMOS-spike.png 512 × 349; 8 KB
Huge circuit.JPG 2,592 × 1,944; 855 KB
I2L-architecture.PNG 320 × 256; 6 KB
IEC compound functional block.svg 248 × 319; 3 KB
IEC output AND dependence ratio.svg 744 × 283; 4 KB
IEC standard logic symbol.svg 744 × 283; 4 KB
IEC terminal inversion symbol.svg 319 × 142; 1 KB
Inverseur commandable avec un masque.png 639 × 272; 10 KB
Inverseur commandable.png 727 × 280; 9 KB
K145IK17 Russian pong style ICs.jpg 320 × 178; 27 KB
Linear phase comparator for NRZ data input var gain.png 1,042 × 577; 52 KB
Listdesberdintasunak.png 1,128 × 531; 339 KB
Logic block2.svg 275 × 75; 12 KB
Logic Nikolay.PNG 315 × 688; 12 KB
Majority Logic.png 572 × 312; 10 KB
Maskin simpel.png 320 × 256; 4 KB
Maskin simpel2.png 320 × 256; 4 KB
Maskin simpel3.png 320 × 256; 5 KB
Maskin simpel4.png 550 × 450; 19 KB
Maskin simpel5.png 550 × 450; 19 KB
Maskin simpel6.png 700 × 600; 31 KB
Measure Delay of an Not Scope 1.svg 156 × 120; 12 KB
Measure Delay of an Not Scope 2.svg 156 × 120; 11 KB
Mfrey Develop Digital Circuit 000 Colored.svg 455 × 410; 24 KB
Mfrey Develop Digital Circuit 000.svg 455 × 410; 24 KB
Mfrey Develop Digital Circuit 001.svg 455 × 410; 22 KB
Mfrey Develop Digital Circuit 002.svg 455 × 410; 17 KB
Mfrey Develop Digital Circuit 003.svg 455 × 410; 13 KB
Mfrey Develop Digital Circuit 004.svg 455 × 410; 9 KB
Mfrey Develop Digital Circuit 005.svg 455 × 410; 5 KB
Mfrey Develop Digital Circuit 100.svg 560 × 500; 28 KB
Mfrey Develop Digital Circuit 101.svg 560 × 500; 28 KB
MFrey Infrared Remote Controll Tester Img1.jpg 1,600 × 1,200; 178 KB
MFrey Infrared Remote Controll Tester Img2.jpg 1,600 × 1,200; 181 KB
MFrey Infrared Remote Controll Tester Img3.jpg 1,600 × 1,200; 195 KB
MFrey Infrared Remote Controll Tester Img4.jpg 1,600 × 1,200; 232 KB
Mfrey remote controller tester parts.jpg 1,600 × 1,200; 412 KB
MFrey TTL Output.svg 240 × 560; 8 KB
Modulator - first order - accumulator - lowpass.svg 765 × 180; 19 KB
Modulator - first order - digital.svg 540 × 180; 18 KB
Modulator - first order - FF.svg 585 × 180; 14 KB
Modulator - first order - integrator - lowpass.svg 765 × 180; 16 KB
Modulator - second order - digital.svg 743 × 225; 28 KB
Omkodare.png 320 × 320; 7 KB
Omkodare2.png 320 × 500; 9 KB
OP-realisering.png 750 × 900; 37 KB
PALASM Design.jpg 552 × 674; 75 KB
PALSolution1.png 420 × 151; 10 KB
PCM euskaraz.png 368 × 195; 7 KB
Por3.png 320 × 256; 3 KB
PRINT 06.TIF 512 × 349; 23 KB
Propositional formula flip flops 1.png 748 × 782; 193 KB
Propositional formula NANDs.png 928 × 800; 236 KB
Propositional formula oscillator 1.png 1,252 × 602; 169 KB
Prototyping board.jpg 600 × 508; 70 KB
Ps2 2octets.png 529 × 408; 56 KB
Ps2 Horloge Compt.png 551 × 201; 30 KB
Register transfer level - example toggler.svg 300 × 200; 8 KB
Register.svg 856 × 189; 68 KB
Remote controll tester.jpg 640 × 480; 93 KB
Sequential logic.GIF 410 × 336; 5 KB
SeñalContinua.PNG 549 × 414; 12 KB
SeñalDiscreta.PNG 556 × 418; 11 KB
