File:JFET Transistor.svg
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Size of this PNG preview of this SVG file: 600 × 210 pixels. Other resolutions: 320 × 112 pixels | 640 × 224 pixels | 1,024 × 358 pixels | 1,280 × 448 pixels | 2,560 × 896 pixels.
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| Description |
Polski: Uproszczona budowa tranzystora polowego złączowego (JFET): S – źródło, D – Dren, G – Bramka, 1 – Ładunek przestrzenny, 2 – Kanał. |
| Date | |
| Source | Na podstawie: Stacewicz T., Kotlicki A., Elektronika w laboratorium naukowym, Wydawnictwo Naukowe PWN, Warszawa 1994, ISBN 83-01-11531-9 |
| Author | Vectorization: Harkonnen² |
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I, the copyright holder of this work, release this work into the public domain. This applies worldwide. In some countries this may not be legally possible; if so: I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law. |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 18:15, 24 June 2007 | | 600 × 210 (9 KB) | Harkonnen2 (talk | contribs) | {{Information |Description=Uproszczona budowa tranzystora polowego złączowego (JFET); S- źródło, D - Dren, G - Bramka; 1. Ładunek przestrzenny, 2. Kanał |Source=Stacewicz T., Kotlicki a., "Elektronika w laboratorium naukowym", Wydawnictwo naukowe P |
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