File:DRAM.svg

English: Organization of a semiconductor Dynamic RAM (DRAM) chip. Each bit of data is stored a memory cell. The cells (blue blocks) are laid out in an array of rows and columns on the chip. The memory address applied to the chip (A) is broken into two parts; a "row address" which is decoded by a row address decoder (green rectangle, left) to select one row of cells, and a "column address" which is decoded by a column address decoder (green rectangle, bottom) to select one of the cells in the active row. When the "Row Address Strobe" (RAS) line is asserted, the row of memory cells is activated, transferring the bit of data in each cell to the sense amplifiers (red blocks). When the "Column Address Strobe" (CAS) line is asserted, the column address decoder picks the bit from one column to output on the "Data" line.