File:31 bit Fibonacci linear feedback shift register.webm

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Original file ‎(WebM audio/video file, VP9, length 30 s, 1,920 × 1,080 pixels, 348 kbps overall, file size: 1.25 MB)

Captions

Captions

A 31 bit max cycle Fibonacci linear feedback shift register with taps at 28 and 31

Summary[edit]

Description
English: A Fibonacci 31 bit linear feedback shift register with taps at positions 28 and 31, giving it a maximum cycle and period at this speed of nearly 6.7 years. The circuit uses 4x74HC565N for the shift registers, a 74HC86N for the XOR and an inverter, and an LMC555 timer for clock pulses.
Date
Source Own work
Author Frussetpouch

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Date/TimeThumbnailDimensionsUserComment
current21:54, 19 June 201930 s, 1,920 × 1,080 (1.25 MB)Frussetpouch (talk | contribs)User created page with UploadWizard

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Transcode status

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Format Bitrate Download Status Encode time
VP9 1080P 1.6 Mbps Completed 21:56, 19 June 2019 1 min 23 s
Streaming 1080p (VP9) 1.6 Mbps Completed 00:20, 13 January 2024 7.0 s
VP9 720P 1.19 Mbps Completed 21:55, 19 June 2019 55 s
Streaming 720p (VP9) 1.19 Mbps Completed 23:39, 16 January 2024 1.0 s
VP9 480P 739 kbps Completed 21:55, 19 June 2019 47 s
Streaming 480p (VP9) 739 kbps Completed 20:23, 16 December 2023 2.0 s
VP9 360P 417 kbps Completed 21:55, 19 June 2019 31 s
Streaming 360p (VP9) 418 kbps Completed 08:22, 17 December 2023 2.0 s
VP9 240P 234 kbps Completed 21:55, 19 June 2019 28 s
Streaming 240p (VP9) 234 kbps Completed 19:59, 8 December 2023 1.0 s
WebM 360P 513 kbps Completed 21:55, 19 June 2019 23 s
Streaming 144p (MJPEG) 1.03 Mbps Completed 23:43, 28 October 2023 5.0 s

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