File:Sipeed Tang Nano 9K FPGA.jpg
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Size of this preview: 800 × 308 pixels. Other resolutions: 320 × 123 pixels | 640 × 247 pixels | 1,280 × 493 pixels.
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Captions
Captions
Sipeed Tang Nano 9K FPGA board
Summary
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| Description |
Français : Carte FPGA Sipeed Tang Nano 9K, basée sur un FPGA Gowin GW1NR-LV9. Un SoC RISC-V Bouffalo BL702 est utilisé pour les communications USB-Série. Il est possible de synthétiser des circuits pour ce FPGA avec les logiciels libres Yosys et son synthétiseur Apicula (Apycula) pour Gowin. Le logiciel libre OpenFPGAloader permet d'y envoyer le bitstream.
English: Sipeed Tang Nano 9K FPGA board, using GW1NR-LV9. A Bouffalo BL702 RISC-V SoC is used for USB-serial communications. This FPGA circuits can be synthesized with open source and free/libre software Yosys and (Gowin dedicated) Apicula (or Apycula). The open source and libre software OpenFPGAloader allow to upload the bitstream on it. |
| Date | |
| Source | Own work |
| Author | Popolon |
Licensing
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I, the copyright holder of this work, hereby publish it under the following license:
 
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This file is made available under the Creative Commons CC0 1.0 Universal Public Domain Dedication. |
| The person who associated a work with this deed has dedicated the work to the public domain by waiving all of their rights to the work worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law. You can copy, modify, distribute and perform the work, even for commercial purposes, all without asking permission.
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| Annotations | This image is annotated: View the annotations at Commons |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 15:14, 28 January 2023 | | 1,280 × 493 (146 KB) | Popolon (talk | contribs) | Uploaded own work with UploadWizard |
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